Title :
A combined successive and Σ-Δ A/D conversion scheme
Author_Institution :
Dept. of Electr. & Electron. Eng., Melbourne Univ., Vic., Australia
Abstract :
A mismatch-insensitive approach to the multi-bit Σ-Δ modulator design is presented. The multi-bit conversion is realized by a successive approximation. A simple controlled averaging technique is introduced to cancel the first-order mismatch error. The cost in circuit complexity increase is very modest
Keywords :
analogue-digital conversion; sigma-delta modulation; A/D conversion scheme; controlled averaging technique; first-order mismatch error; mismatch-insensitive approach; multi-bit conversion; multibit, sigma-delta modulator; oversampling; successive approximation; Additive noise; Bandwidth; Circuit noise; Complexity theory; Digital filters; Error correction; Noise shaping; Quantization; Sampling methods; Signal resolution;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.393967
