VLSI implementation of real-time image segmentation

Modified Canny edge detector for image segmentation is proposed for VLSI implementation. FPGA is considered to realize the modified canny edge detector. Processed results of test images are presented to illustrate the performance capabilities of the proposed approach. Canny edge detector treats edge detection as a signal processing problem to design an optimal edge detector and has been widely used for edge detection. A pipelined implementation on FPGA for modified version of this algorithm is proposed MATLAB simulation results are given. A newfangled method for segmentation of 2-D imagery that uses best alternative approach for image enhancement as well as edge-detection is proposed.