DocumentCode
2608837
Title
Modeling MOSFET and circuit degradation through SPICE
Author
Cester, Andrea ; Gerardin, Simone ; Paccagnella, Alessandro ; Ghidini, Gabriella
Author_Institution
DEI, Universitadi Padova, Italy
fYear
2005
fDate
12-16 Sept. 2005
Firstpage
403
Lastpage
406
Abstract
In this work we investigate the impact of MOSFET degradation on the operation of real circuits through SPICE simulation. We show that by changing a few parameters in a LEVEL 3 model it is possible to reasonably account for the degradation in the characteristics of a single device following electrical stress. We then validate this approach on a simple circuit, a current mirror, and finally analyze the degradation of a more complex one, a voltage controlled oscillator.
Keywords
MOSFET; MOSFET circuits; SPICE; semiconductor device models; MOSFET degradation; SPICE simulation; circuit degradation; current mirror; electrical stress; voltage controlled oscillator; CMOS technology; Circuit simulation; Degradation; MOSFET circuits; Microelectronics; Mirrors; Monitoring; SPICE; Stress; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European
Print_ISBN
0-7803-9203-5
Type
conf
DOI
10.1109/ESSDER.2005.1546670
Filename
1546670
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