Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability

Author

Lim, K.Y. ; Chan, V. ; Rengarajan, R. ; Lee, H.K. ; Rovedo, N. ; Lim, E.H. ; Yang, S. ; Jamin, F. ; Nguyen, P. ; Lin, W. ; Lai, C.W. ; Teh, Y.W. ; Lee, J. ; Kim, L. ; Luo, Z. ; Ng, H. ; Sudijono, J. ; Wann, C. ; Yang, I.

Author_Institution

Chartered Semicond. Manuf. Ltd., Singapore

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

415

Lastpage

418

Abstract

In this paper, a study on middle-of-line (MOL) process on transistor performance and reliability was presented based on 300mm experimental data. The major MOL parameters that are affecting device performance and reliability are MOL thermal expense and mechanical stress from contact etches stop nitride liner. Based on the study, we had developed a robust 45nm gate-length CMOSFET for 90nm node high performance application. Aggressive gate length and gate dielectric scaling along with optimized MOL engineering has proven high performance devices similar to 65nm node CMOSFET (Nakahara et al., 2003).

Keywords

MOSFET; nanotechnology; semiconductor device breakdown; semiconductor device reliability; 45 nm; 65 nm; 90 nm; CMOSFET; MOL engineering; MOL thermal expense; contact etches; mechanical stress; middle-of-line temperature; transistor performance; transistor reliability; CMOSFETs; Dielectric devices; Etching; MOSFET circuits; Optical noise; Optical scattering; Performance gain; Plasma temperature; Semiconductor device reliability; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European

Print_ISBN

0-7803-9203-5

Type

conf

DOI

10.1109/ESSDER.2005.1546673

Filename

1546673