DocumentCode :
2608924
Title :
Post clean elimination at backgrind
Author :
Phaoharuhan, P.
Author_Institution :
AMD(Thailand) Ltd.
fYear :
2003
fDate :
10-12 Dec. 2003
Firstpage :
663
Lastpage :
666
Abstract :
This paper summarizes the methodology and impact of a 2-phase benchmark process improvement project to eliminate cleaning at backgrinding operations, and to qualify a new type of ´washless´ BG tape. The project was initiated to eliminate wafer breakage at the cleaning operation, and reduce/eliminate Non Stick on Pad (NSOP) at wire bonding as a result of voids caused by chemical reactions of DI water and tape residue on bond pads. The project involved an engineering feasibility study of eliminating cleaning at backgrinding. Experiments were carried out with dummy wafers to evaluate the impact of washless backgrinding on assembly criteria. The conclusion of the study recommended to start a qualification process using production wafers and verify the impact on test yield and reliability as well as assembly quality. The second phase of the project was added to the original project plan after a tape supplier announced the launch of a new type of ´washless´ tape. The team,therefore, carried out detailed analyses of the properties of the tape, and completed a qualification process that culminated in 100 percent implementation of the new type of tape for production. Immediate impacts and benefits of the implementation of the new ´washless´ tape include a projected BG tape cost reduction, maintained very high Cpk at most assembly quality indices, elimination of NSOP due to voids from residue on bond pads, and improved assembly yield. Elimination of the cleaning process at backgrinding is expected to have business competitiveness through substantial assembly cycle time reduction, elimination of wafer breakage at BG cleaning, reduced NSOP at wire bonding, and generally improve product quality, yield, and customer satisfaction.
Keywords :
integrated circuit packaging; integrated circuit yield; lead bonding; surface cleaning; assembly quality; backgrinding operations; cycle time reduction; engineering feasibility; integrated circuit packages; nonstick on pad; post clean elimination; qualification process; tape residue; test yield; two-phase benchmark process improvement; voids; wafer breakage; washless tape; wire bonding; Assembly; Chemicals; Cleaning; Costs; Production; Qualifications; Reliability engineering; Testing; Wafer bonding; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology, 2003 5th Conference (EPTC 2003)
Print_ISBN :
0-7803-8205-6
Type :
conf
DOI :
10.1109/EPTC.2003.1271602
Filename :
1271602
Link To Document :
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