DocumentCode
2609009
Title
Simulation of fatigue life of solder ball joints of an ultra-fine-pitch wafer level package
Author
Zhao, Bin
Author_Institution
Fac. of Eng., Nat. Univ. of Singapore, Singapore
fYear
2003
fDate
10-12 Dec. 2003
Firstpage
683
Lastpage
686
Abstract
With the relentless trend towards ever increasing number of I/Os for IC packages, pitches of flip chip packages are becoming every smaller. With smaller pitches and smaller stand-offs, the fatigue life of solder joints are expected to decrease. It is well known that the corner solder joint which is furthest from the centre of the package (called the critical solder joint) is usually the first to fail owing to the largest strain ranges experienced there. This paper describes a finite element study of the fatigue life of the critical solder ball joint of a 20 mm×20 mm flip chip package with a ball pitch of 100 μm. Due to the large number of joints required to be analysed, a submodeling method is employed. In this method, a thin slice of the package is first modeled with relatively coarse meshes. From this analysis, the displacements of the top and bottom interfaces of the solder ball joint will be obtained and then used as boundary conditions for a finite element analysis of the critical solder joint using very fine meshes. The effect of underfills are studied. Some popular models for predicting fatigue life of solder joints such as Solomon´s and Engelmaier´s are described and the results for the package under study presented and compared.
Keywords
encapsulation; fine-pitch technology; flip-chip devices; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; mesh generation; thermal stress cracking; 100 micron; 20 mm; Engelmaier model; Solomon model; ball pitch; critical solder joint strain; finite element study; flip chip packages; mesh modeling; solder ball joint fatigue life; stand-off height; thermal fatigue; ultra-fine-pitch package; underfills; wafer level package; Capacitive sensors; Costs; Fatigue; Finite element methods; Flip chip; Integrated circuit packaging; Packaging machines; Soldering; Temperature; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology, 2003 5th Conference (EPTC 2003)
Print_ISBN
0-7803-8205-6
Type
conf
DOI
10.1109/EPTC.2003.1271606
Filename
1271606
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