Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

Author

Dixit, A. ; Anil, K.G. ; Rooyackers, R. ; Kaiser, M. ; Weemaes, R. ; Ferain, I. ; De Keersgieter, A. ; Collaert, N. ; Surdeanu, R. ; Goodwin, M. ; Zimmerman, P. ; Loo, R. ; Caymax, M. ; Jurczak, M. ; Biesemans, S. ; De Meyer, K. ; Leys, F.

Author_Institution

IMEC, Heverlee, Belgium

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

445

Lastpage

448

Abstract

High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate devices with narrow fins. This makes selective epitaxial growth of Si in the S/D regions, the enabling process for multiple gate CMOS technologies. In this paper, we endeavor to integrate a low temperature selective epitaxial growth process and a low temperature NiSi process to form low resistance S/D contacts. Our experimental results show 34% and 11% improvement in parasitic S/D resistance of N-and P-channel multiple gate FETs with less than 20 nm wide fins respectively.

Keywords

CMOS integrated circuits; contact resistance; electrical contacts; epitaxial growth; field effect transistors; nickel compounds; 20 nm; CMOS technologies; NiSi; contact resistance; epitaxial growth process; multiple gate FET; multiple gate devices; narrow fins; CMOS process; CMOS technology; Circuits; Contact resistance; Diffusion processes; Epitaxial growth; FETs; Instruments; Shape; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European

Print_ISBN

0-7803-9203-5

Type

conf

DOI

10.1109/ESSDER.2005.1546680

Filename

1546680