The effects of memory-access ordering on multiple-issue uniprocessor performance

We study the effect of memory access ordering policies on processor performance. Relaxed ordering policies increase available instruction-level parallelism, but such policies must be evaluated subject to their effect on memory consistency-since virtually all microprocessors are designed to be compatible with shared memory multiprocessor systems, even uniprocessor desktop computers are constrained by the rules of multiprocessor memory consistency models. We define the set of potential parallelism-restricting ordering rules found in strong memory models. We then construct a spectrum of possible memory models by progressively relaxing these restrictions. Some of our models are similar to those of existing commercial processors, other models illustrate potential alternatives. We simulate and analyze several uniprocessor benchmarks from the SPEC95 and SPLASH-2 suites using a super scalar processor simulator (Armadillo) developed at the University of Texas at Austin. This simulator models dataflow instruction execution, branch prediction, speculative execution, memory disambiguation and an aggressive memory system. Our experiments confirm the significant benefits of a weaker memory model on processor performance. Although the absolute performance varies considerably from benchmark to benchmark, the relative performance gains of relaxing specific memory ordering constraints is surprisingly similar across most of the benchmarks