Design of decimation filter for real-time signal processing of micro-air-vehicles

This paper reports a digital decimation filter chip for real-time signal processing of micro-air-vehicles (MAVs), which is composed of cascade integrator comb (CIC) filter, half-band filter and CIC compensation filter. To obtain low power, low hardware cost and efficient area, optimization was performed at behavioral level modeling and register transfer level (RTL) design. A mathematical framework was presented to perform parameters optimization of different filters. The layout was designed based on SMIC 0.18 μ m process library. The verification results show that the chip achieves a signal to noise ratio (SNR) of 54.40dB. The chip area occupies 1.69mm² and dissipates only 2.95mW power. Area and power are well satisfied with the separation point detection of MAVs´ boundary layer.