DocumentCode
2609333
Title
Finite element simulation of thermomechanical stress evolution in Cu/low-k interconnects during manufacturing and subsequent thermal cycling
Author
Chérault, Nathalie ; Besson, Jacques ; Goldberg, Cindy ; Casanova, Nicolas ; Berger, Marie-Hélène
Author_Institution
Centre des Materiaux, Ecole des Mines de Paris, Evry, France
fYear
2005
fDate
12-16 Sept. 2005
Firstpage
493
Lastpage
496
Abstract
The integration of low-k interlayer dielectrics in interconnects is associated with an increase in mechanical reliability risks. Thermomechanical stresses must be evaluated to understand the behavior of interconnects. As manufacturing processes can introduce large stresses, a sequential process modeling technique is developed in this study. The constituent materials of the interconnects are described by a single elasto-plastic constitutive equation developed from substrate curvature measurements. Stresses in Cu/low-k lines are also evaluated. A good correlation between finite element modeling and curvature measurements is obtained.
Keywords
annealing; etching; finite element analysis; integrated circuit interconnections; low-k dielectric thin films; manufacturing processes; stress effects; thermal stresses; thermomechanical treatment; finite element simulation; interconnects; low-k interlayer dielectrics; manufacturing processes; mechanical reliability risks; process modeling technique; single elasto-plastic constitutive equation; substrate curvature measurements; thermal cycling; thermomechanical stress; Copper; Dielectric materials; Dielectric measurements; Dielectric substrates; Finite element methods; Integrated circuit interconnections; Manufacturing processes; Thermal stresses; Thermomechanical processes; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European
Print_ISBN
0-7803-9203-5
Type
conf
DOI
10.1109/ESSDER.2005.1546692
Filename
1546692
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