Experimental and theoretical study of layered tunnel barriers for nonvolatile memories

Engineering of the tunnel barrier of nonvolatile memories (NVM) is addressed in this paper. This work reports in its first part experimental results that show the improved field sensitivity of the gate current of MOS devices with SiO₂/HfO₂ gate stacks compared to SiO₂ of identical electrical thickness (EOT). This improvement is justified by tunneling current simulations. The physical principle that is involved is applicable to symmetrical triple-layer tunnel barriers consisting of SiO₂/HfO₂/SiO₂ which could equally favor writing and erasing of NVM devices. The second part of this paper presents an original study of the programming and retention characteristics of triple-layer SiO₂/high-k/SiO₂ tunnel barriers with a 5nm EOT. Our calculations allow to clearly view the influence of the high-k parameters on programming and data retention. According to our results, good characteristics are obtained for dielectrics with a 1.5eV conduction band offset compared to Si and for ε _high-k √m_high-k >(4m_high-k: relative electron mass ε _high-k: relative dielectric constant). These conditions are verified by the physical parameters of HfO₂.