STI-induced damage and hot-carrier reliability in the narrow width short channel NMOSFET fabricated using global strained-Si technology

Author

Phua, W.H.T. ; Ang, D.S. ; Ling, C.H. ; Chui, K.J.

Author_Institution

Dept. of Electr. & Electron. Eng., Singapore Nat. Univ., Singapore

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

533

Lastpage

536

Abstract

The width dependence of threshold voltage (V_t) in the strained-Si NMOSFET relative to that of the control bulk Si device is examined. The contrasting behavior of V_t, for decreasing channel width (W_drawn) at a given channel length (L_drawn), could be ascribed to the increased concentration of the channel dopant at the regions near the STI (shallow trench isolation)/gate edge of the strained device. Dopant enhancement is attributed to the abundance of interstitial defect sites located in both the strained-Si and the SiGe layer, due to the lattice strain arising from the STI process. Hot-carrier degradation is found to be marginally higher in the narrow-width strained device.

Keywords

Ge-Si alloys; MOSFET; elemental semiconductors; hot carriers; isolation technology; semiconductor device reliability; semiconductor doping; silicon; NMOSFET; SiGe; channel dopant; hot carrier degradation; interstitial defect sites; lattice strain; reliability; shallow trench isolation; strained Si technology; Capacitive sensors; Degradation; Germanium silicon alloys; Hot carriers; Lattices; MOSFET circuits; Silicon germanium; Strain control; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European

Print_ISBN

0-7803-9203-5

Type

conf

DOI

10.1109/ESSDER.2005.1546702

Filename

1546702