DocumentCode
2609661
Title
Double edge triggered devices: Speed and power constraints
Author
Hossain, Razak ; Wronski, Leszek ; Albicki, Alexander
Author_Institution
Dept. of Electr. Eng., Rochester Univ., NY, USA
fYear
1993
fDate
3-6 May 1993
Firstpage
1491
Abstract
A new set of double edge triggered flip-flops has been developed. It requires fewer transistors to implement than earlier designs. The energy consumption in the authors´ double edge triggered flip-flops is shown to be lower than in single edge triggered (SET) flip-flops. This is demonstrated by architecture level analysis, circuit analysis and simulation techniques. The maximum data rate in double and single edge triggered flip-flops is also compared via simulation
Keywords
circuit analysis computing; flip-flops; logic CAD; architecture level analysis; circuit analysis; double edge triggered flip-flops; energy consumption; maximum data rate; power constraints; simulation techniques; speed constraints; Analytical models; Circuit analysis; Circuit simulation; Clocks; Energy consumption; Flip-flops; Frequency; MOSFETs; Power dissipation; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.394017
Filename
394017
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