DocumentCode
2609728
Title
On the resetability of synchronous sequential circuits
Author
Lioy, A. ; Poncino, M.
Author_Institution
Dip. Autom. e Inf., Politecnico di Torino, Italy
fYear
1993
fDate
3-6 May 1993
Firstpage
1507
Abstract
An improved three-valued simulation method is presented. It is based on implicit enumeration of primary inputs, and computes the resetability, the set of reset states, and the set of reachable states for synchronous sequential circuits. Efficient topological heuristics are used to reduce the number of enumerations, and to guide the selection of primary inputs. This leads to the computation of the reset sequences for several standard benchmarks
Keywords
binary sequences; circuit analysis computing; digital simulation; network topology; sequential circuits; enumerations; implicit enumeration; primary inputs; reachable states; reset sequences; reset states; resetability; standard benchmarks; synchronous sequential circuits; three-valued simulation method; topological heuristics; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Data structures; Hardware; Memory management; Sequential circuits; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.394021
Filename
394021
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