DocumentCode
2609803
Title
Functional testing and constrained synthesis of sequential architectures
Author
Buonanno, G. ; Fummi, F. ; Sciuto, D.
Author_Institution
Dipartimento di Elettronica, Politecnico di Milano, Italy
fYear
1993
fDate
3-6 May 1993
Firstpage
1523
Abstract
A new approach is presented for test pattern generation for finite state machines and the relationships with their gate level implementation. The results on a study on implementation constraints that will guarantee a fixed fault coverage are presented. The proposed techniques are checked through some MCNC benchmarks and their results are compared with previous papers
Keywords
automatic testing; finite state machines; integrated circuit testing; logic testing; sequential circuits; MCNC benchmarks; constrained synthesis; finite state machines; fixed fault coverage; gate level implementation; implementation constraints; sequential architectures; test pattern generation; Automata; Benchmark testing; Concatenated codes; Constraint optimization; Sequential analysis; Tail; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.394025
Filename
394025
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