An accurate delay model for BiCMOS gates and off-chip drivers

A delay model for BiCMOS inverters and drivers is reported. This model combines two important features. First, it is valid for a wide range of load capacitances, i.e., from sub-picofarads to tens of picofarads. The model accounts for most of the important device phenomena especially the dependence of the current gain and the forward transit time of the bipolar junction transistors (BJTs) on the collector current level. The second feature is that the model yields accurate closed form expressions for the 50% fall and rise times. The error between the analytical model and simulation program with IC emphasis (SPICE) is for most cases within 10%. The proposed closed form delay expression can be used reliably for device and circuit design applications