Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores

Built-in self-repair (BISR) architectures and methods are widely used for memory cores of system-on-chips (SoCs), where the area-efficient fault detection and repair are crucial in order to meet the high quality requirements. Research of BISR architectures for logic cores has begun as well. However, the irregular structure of logic cores represents a serious limitation and therefore, currently only ad hoc methods exist. Automated generation of BISR architectures for random logic SoC cores is proposed in this paper. The generation is guided by the characteristics of the architecture: mean time to failure (MTTF) and area overhead. The main contribution is the fully automated handling of arbitrary random logic cores and the possibility to generate architectures based on various BISR principles. The proposed method was implemented and evaluated over benchmark circuits, and the experiments confirmed that BISR architectures can be successfully generated for random logic cores. The MTTFs of the generated architectures have been improved at the cost of relatively low area overhead.