Title :
Comprehensive modeling of VLSI test
Author :
Ziaja, Thomas ; Swartzlander, Earl, Jr.
Author_Institution :
IBM Corp., Austin, TX, USA
Abstract :
Predictive models for test traditionally focus on the defect level leaving the test process, while ignoring the Type I error which occurs when the test fails good circuits. This paper presents a general framework for understanding test processes, all of which exhibit both Type I and Type II errors. The application of this framework to published models for test is developed within this general framework, illustrating its usefulness in describing various types of tests. The use of this framework in including the effect of Type I error is then demonstrated and references to its application, including Type I error, to an actual manufacturing test process are provided
Keywords :
VLSI; errors; integrated circuit testing; modelling; production testing; VLSI test modelling; errors; manufacturing test process; predictive models; Circuit testing; Computer errors; Fabrication; Integrated circuit manufacture; Integrated circuit modeling; Integrated circuit yield; Manufacturing processes; Predictive models; Very large scale integration; Virtual manufacturing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-8186-7545-4
DOI :
10.1109/DFTVS.1996.572021
