Title :
A fault-tolerant DCT-architecture based on distributed arithmetic
Author :
Gaedke, Klaus ; Franzen, Jens ; Pirsch, Peter
Author_Institution :
Lab. fuer Inf., Hannover Univ., Germany
Abstract :
A fault-tolerant discrete cosine transform (DCT)-architecture based on distributed arithmetic is developed. Fault-tolerance is achieved through a combination of distributed and residue arithmetic units. The implementation area of the presented architecture is about twice the size of a standard, non-fault-tolerant realization. Simulations on gate-level show that about 75% of the logic area is protected against single static or dynamic stuck-at faults
Keywords :
data compression; digital arithmetic; digital signal processing chips; discrete cosine transforms; fault tolerant computing; residue number systems; arithmetic units; discrete cosine transform; distributed arithmetic; fault-tolerant DCT-architecture; gate-level simulation; logic area; stuck-at faults; Arithmetic; Clocks; Discrete cosine transforms; Equations; Fault tolerance; Read only memory; Registers; Throughput; Very large scale integration; Video compression;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394040
