DocumentCode
261013
Title
A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth
Author
Woorham Bae ; Deog-Kyoon Jeong
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea
fYear
2014
fDate
15-18 Jan. 2014
Firstpage
1
Lastpage
2
Abstract
A technique making the loop bandwidth consistent against PVT variations in the ring-VCO based bang-bang PLL/CDR is proposed. Pulse generators are used to implement this technique by cancelling out PVT sensitivity of the ring-VCO. Simulation results show that the loop bandwidth variation is reduced by half with the proposed technique. Also, by using the pulse generators, the loop filter capacitor area is reduced.
Keywords
clock and data recovery circuits; phase locked loops; pulse generators; voltage-controlled oscillators; CDR; PVT variations; bang-bang PLL; clock and data recovery; loop bandwidth variation; loop filter capacitor area; phase-locked loops; pulse generators; ring-VCO design; voltage-controlled oscillator; Bandwidth; Clocks; Filtering theory; Phase locked loops; Pulse generation; Sensitivity; Voltage-controlled oscillators; CDR; PLL; PVT variations; loop bandwidth; ring-VCO;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Information and Communications (ICEIC), 2014 International Conference on
Conference_Location
Kota Kinabalu
Type
conf
DOI
10.1109/ELINFOCOM.2014.6914430
Filename
6914430
Link To Document