A parametric design of a built-in self-test FIFO embedded memory

Author

Barbagallo, S. ; Bodoni, M. Lobetti ; Medina, D. ; Blasio, G. De ; Ferloni, M. ; Fummi, F. ; Sciuto, D.

Author_Institution

DSRC, Italtel Soc. Italiana Telecommun. SpA, Milan, Italy

fYear

1996

fDate

6-8 Nov 1996

Firstpage

221

Lastpage

229

Abstract

Aim of this paper is to present a self-testable FIFO memory macrocell, which can be embedded into larger devices. A dual port RAM-type NFO has been designed. A new test procedure for the macrocell has been defined aiming at detecting all possible faults in the control logic and the RAM cell. Given such a test procedure the appropriate Built-in Self Test architecture has been defined, independently of the memory size. Fault coverage and area overhead for the proposed solution are presented

Keywords

built-in self test; integrated circuit design; integrated circuit testing; integrated memory circuits; random-access storage; FIFO embedded memory; RAM cell; area overhead; built-in self-test; control logic; dual port FIFO; fault coverage; macrocell; parametric design; Automatic testing; Built-in self-test; Fault detection; Logic devices; Logic testing; Macrocell networks; Random access memory; Read-write memory; Telecommunications; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1996. Proceedings., 1996 IEEE International Symposium on

Conference_Location

Boston, MA

ISSN

1550-5774

Print_ISBN

0-8186-7545-4

Type

conf

DOI

10.1109/DFTVS.1996.572028

Filename

572028