DocumentCode :
2610403
Title :
Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes
Author :
Jafri, Syed M A H ; Guang, Liang ; Hemani, Ahmed ; Paul, Kolin ; Plosila, Juha ; Tenhunen, Hannu
Author_Institution :
R. Inst. of Technol., Stockholm, Sweden
fYear :
2012
fDate :
5-8 Sept. 2012
Firstpage :
242
Lastpage :
249
Abstract :
This paper presents an energy efficient architecture to provide on-demand fault tolerance to multiple traffic classes, running simultaneously on single network on chip (NoC) platform. Today, NoCs host multiple traffic classes with potentially different reliability needs. Providing platform-wide worst-case (maximum) protection to all the classes is neither optimal nor desirable. To reduce the overheads incurred by fault tolerance, various adaptive strategies have been proposed. The proposed techniques rely on individual packet fields and operating conditions to adjust the intensity and hence the overhead of fault tolerance. Presence of multiple traffic classes undermines the effectiveness of these methods. To complement the existing adaptive strategies, we propose on-demand fault tolerance, capable of providing required reliability, while significantly reducing the energy overhead. Our solution relies on a hierarchical agent based control layer and a reconfigurable fault tolerance data path. The control layer identifies the traffic class and directs the packet to the path providing the needed reliability. Simulation results using representative applications (matrix multiplication, FFT, wavefront, and HiperLAN) showed up to 95% decrease in energy consumption compared to traditional worst case methods. Synthesis results have confirmed a negligible additional overhead, for providing on-demand protection (up to 5.3% area), compared to the overall fault tolerance circuitry.
Keywords :
fast Fourier transforms; fault tolerance; integrated circuit reliability; matrix algebra; network-on-chip; FFT; HiperLAN; NoC; energy consumption; energy efficient architecture; energy-aware fault-tolerant network-on-chips; hierarchical agent based control layer; individual packet fields; matrix multiplication; multiple traffic classes; on-demand fault tolerance; overall fault tolerance circuitry; platform-wide worst-case protection; reconfigurable fault tolerance data path; reliability; Circuit faults; Computer architecture; Fault tolerance; Fault tolerant systems; Switches; Wires; Energy Aware Systems; Fault Tolerance; Network on Chips; Self Adaptive systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2012 15th Euromicro Conference on
Conference_Location :
Izmir
Print_ISBN :
978-1-4673-2498-4
Type :
conf
DOI :
10.1109/DSD.2012.49
Filename :
6386897
Link To Document :
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