Title :
Architecture of a FPGA-based coprocessor: the PAR-1
Abstract :
The implementation of a FPGA based coprocessor and its programming methodology are shown. The effects of different sequencing models, and regular and irregular circuits on the hardware and in the programming methodology are discussed. Two examples are described: a sorting network and the kernel of a speech recognition algorithm. The results are still preliminary but they suggest some architectural improvements for general FPGA based computing machines
Keywords :
computer architecture; coprocessors; field programmable gate arrays; microprogramming; FPGA based coprocessor; FPGA-based coprocessor; PAR-1; architectural improvements; general FPGA based computing machines; irregular circuits; programming methodology; regular circuits; sequencing models; sorting network; speech recognition algorithm; Application software; Circuits; Coprocessors; Delta modulation; Field programmable gate arrays; Hardware; Logic programming; Master-slave; Prototypes; Software prototyping;
Conference_Titel :
FPGAs for Custom Computing Machines, 1995. Proceedings. IEEE Symposium on
Conference_Location :
Napa Valley, CA
Print_ISBN :
0-8186-7548-9
DOI :
10.1109/FPGA.1995.477405
