Design methodology of VLSI with multiple valued logic

There has not been a widespread adoption of multiple valued logic (MVL) due to the unclear status of the appropriate design methodology for VLSI systems based on MVL. This problem is addressed discussing both system and circuit design methodology. It is argued that logic synthesis, which is problematic for higher radices, need not be a central design activity as arithmetic functional blocks can be specified as piecewise linear functions. Alternative methodologies for these are presented. They consist of sets of primitive building blocks and rules for their composition