A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs

As planar scaling to achieve higher chip integration seems to be on the brink of saturation, three-dimensional (3D) integration has emerged as a promising technology. It is critical to have efficient early stage estimation methodologies to build high performance digital systems as well as to shorten design time. In this paper, a novel methodology is proposed which takes into account key physical effects and explores Through-Silicon-Via (TSV) placement topologies for a 2-tier 3D stack. It estimates the interconnect electrical performance and TSV area penalty across two TSV performance corners. The methodology offers flexibility in selection of the CMOS technology node and the 3D stacking level. A SystemC implementation provides for parameterizability and modeling with ease and also enables integration into a high-level system simulation framework. Using our methodology, TSV placement topologies were explored for a 7-port 3D router. Our results present optimal topologies for the router for typical 45 nm and 32 nm technology nodes. They also point out unreliable topologies and give important feedback for 3D system design.