Video decimator design using a systolic array

The decimation of video signals from the National Television System Committee (NTSC) composite video format to the common interchange format (CIF) is discussed. This conversion is necessary to interface standard cameras with a new AT&T P × 64 codec chip set. The decimator circuit is designed based on a systolic array and is implemented using a field programmable gate array (FPGA). The systolic architecture aids in handling the large video bandwidth and allows the use of FPGA technology which has a relatively large propagation delay