• DocumentCode
    261092
  • Title

    MUX-based design of DPLL for wireless communication

  • Author

    Bhattacharyya, Sabyasachi ; Sarma, Ripunjoy ; Bhattacharyya, Kaustubh ; Ahmed, Ragib Nasir ; Saikia, Roushan

  • Author_Institution
    Dept. of Electron. & Commun. Eng., Assam down town Univ., Guwahati, India
  • fYear
    2014
  • fDate
    27-28 Feb. 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    For modern day communication devices, the key aspect lies in the proper reception of data at minimum possible error rates and also on maintenance of great degrees of precision. But, while doing so, a very important aspect that should be kept in mind is the ability of the device developed to operate at reasonable speeds, because it must be compatible with the other sub-systems of the communication setup. Also, the design complexity of the device and the cost of design should be minimum. By putting all these factors together, we can define a common term called time complexity which is the main concern of this proposed work. Considering the various constraints at hand, we would like to propose the design of a Multiplexer-based DPLL device which comprises of features such as good speed, simplified design and precise reception of data.
  • Keywords
    computational complexity; digital phase locked loops; multiplexing equipment; radiocommunication; MUX-based design; multiplexer-based DPLL device; time complexity; wireless communication; Clocks; Detectors; Educational institutions; Phase locked loops; Synchronization; Voltage-controlled oscillators; detector; multiplexer; oscillator; phase; recovery;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Information Communication and Embedded Systems (ICICES), 2014 International Conference on
  • Conference_Location
    Chennai
  • Print_ISBN
    978-1-4799-3835-3
  • Type

    conf

  • DOI
    10.1109/ICICES.2014.7033978
  • Filename
    7033978