Title :
Compact and fast multiplier using dual array tree structure
Author :
Park, Min C. ; Lee, Bang W. ; Kim, Gwang M. ; Kim, Dong H.
Author_Institution :
Samsung Electronic Co., KyungGi-Do, South Korea
Abstract :
A parallel multiplier topology with compact area and fast speed is presented. This new architecture includes dual partial product arrays, which are divided from one partial product plane of a conventional array multiplier. Due to parallel operation of this proposed dual array, multiplication speed is increased twice. Outputs of both arrays are summed with a binary tree adder, while each partial product array is made with full adders. This proposed multiplier fabricated in a 1.0-μm double metal CMOS process, operates at 16 nSec in the worst case of 70°C and 4.75 volt power voltage
Keywords :
CMOS digital integrated circuits; adders; multiplying circuits; parallel architectures; 1.0 micron; 16 ns; 4.75 V; 70 degC; binary tree adder; double metal CMOS process; dual array tree structure; dual partial product arrays; multiplication speed; parallel multiplier topology; CMOS process; Circuit topology; Clocks; Digital signal processing; Digital signal processors; Pipelines; Reduced instruction set computing; Tree data structures; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
Chicago, IL
Print_ISBN :
0-7803-1281-3
DOI :
10.1109/ISCAS.1993.394099
