Distance-Constrained Force-Directed Process Mapping for MPSoC Architectures

In this paper, we present a novel approach for automated mapping of software processes onto the cores of MPSoC architectures using a regular packet-based communication infrastructure. During the mapping determination, the communication distance as well as the routing algorithm for packet-based communication are taken into account. The basic idea of the developed approach is the reduction of communication conflicts on the communication network links for reducing the overall communication latency and hence for increasing the total system performance. The presented approach is based on the idea of force-directed scheduling (FDS) from high-level synthesis and uses forces for determining an optimized process mapping. The approach constrains the cores, that are used for the calculation of possible mappings, by the communication distance of the communicating processes. We present results obtained from an advanced driver assistance system on a Tilera TILEPro64 processor.