Methodology for the design of signed-digit DSP processors

A generalized systematic graph-based methodology for designing novel architectures based on signed-digit representation is introduced. The proposed methodology starts from the algorithmic level and ends with implementation at the digit level. Taking into account the target architecture, the dependence graph of the algorithm is described by a set of uniform recurrent equations. Depending on the target architecture, regular or tree array architectures are derived, which demonstrates low latency and high throughput rates. Several designs are presented. They exhibit regularity, modularity, and local interconnections, being suitable for VLSI implementation. The methodology is demonstrated by the design of an array multiplier