KaGen-A generator of static CMOS-cell layout from circuit schematics

Author

Doerffer, K. ; Téby, Attila T. ; Anton, Oskar ; Mlynski, Dieter A.

Author_Institution

Inst. fuer Theoretische Elektrotechn. & Messtech., Karlsruhe Univ., Germany

fYear

1993

fDate

3-6 May 1993

Firstpage

1845

Abstract

KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a transfer gate). The system operates in three stages. The circuit is positioned into subcircuits. For each subcircuit, a set of layout-candidates for an optimal cell is generated. In the last step, the cells are placed. During placement, the best fitting cells are chosen from the set of layout-candidates

Keywords

CMOS integrated circuits; circuit layout CAD; circuit optimisation; integrated circuit layout; logic CAD; KaGen; cell height; circuit schematics; dual series-parallel CMOS circuits; functional CMOS cells; layout generator; optimal cell; placement; static CMOS-cell layout; subcircuits; width optimization; Algorithm design and analysis; CMOS logic circuits; Collision mitigation; Digital signal processing; Minimization methods; Neodymium; Partitioning algorithms; Strips; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394106

Filename

394106