Layout compaction with minimized delay bound on timing critical paths

Author

Wang, Lih-Yang ; Lai, Yen-Tai ; Liu, Bin-Da ; Chang, Tin-Chung

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

1993

fDate

3-6 May 1993

Firstpage

1849

Abstract

A layout compaction problem which aims at both performance improvement and area reduction is studied. A new algorithm which first determines the minimal delay bound for performance critical paths and then minimizes the layout size without affecting the previous consideration is proposed. These two steps are formulated as two linear programs and solved by the simplex algorithm. Effective graph-based techniques for finding the initial solution and reducing the problem dimension are employed in order to reduce the execution time

Keywords

VLSI; circuit layout CAD; delays; linear programming; logic CAD; logic design; network routing; timing; area reduction; execution time; graph-based techniques; layout compaction problem; layout size; linear programs; minimized delay bound; performance critical paths; performance improvement; problem dimension; simplex algorithm; timing critical paths; Clocks; Compaction; Councils; Delay; Flip-flops; Integrated circuit interconnections; Minimization; Routing; Timing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394107

Filename

394107