Reconfiguration of 1½ track-switch mesh-arrays with PE and bus faults

The mesh-connected processor array model using 1½ track-switches has an advantage of its inherent simplicity of the routing hardware. In this paper, for the model, we investigate its fault tolerant ability for simultaneous processor element (PE) and bus faults. First, we discuss how interconnections are restructured, avoiding faulty PE and buses. Then, we present a neural algorithm for reconfiguration, using a Hopfield-type neural network model. We show the influence of bus faults on the reliabilities of arrays by simulation. The proposed neural algorithm has an advantage that the computation time for reconstruction is so small. Furthermore, the algorithm has a potentiality that a built-in self-reconfigurable system may be realized by implementing the algorithm by hardware in a less complicated way