Design methodologies for partially reconfigured systems

Author

Hadley, J.D. ; Hutchings, B.L.

Author_Institution

Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA

fYear

1995

fDate

19-21 Apr 1995

Firstpage

78

Lastpage

84

Abstract

Run time reconfiguration (RTR) as an implementation approach that divides an application into a series of sequentially executed stages with each stage implemented as a separate circuit module. Partial RTR extends this approach by partitioning these stages and designing their circuit modules such that they exhibit a high degree of functional and physical commonality. Transitioning between configurations can then be accomplished by updating only the differences between configurations. This reduces the amount of time that an RTR application spends configuring and significantly enhances overall performance. The paper presents the design methodology for partial RTR in the context of RRANN2, a partial RTR artificial neural network

Keywords

field programmable gate arrays; logic CAD; logic partitioning; neural nets; reconfigurable architectures; RRANN2; RTR application; circuit modules; design methodologies; design methodology; implementation approach; partial RTR artificial neural network; partially reconfigured systems; physical commonality; run time reconfiguration; separate circuit module; sequentially executed stages; Application software; Artificial neural networks; Circuits; Design methodology; Field programmable gate arrays; Logic functions; Programmable logic arrays; Prototypes; Reconfigurable logic; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1995. Proceedings. IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-7548-9

Type

conf

DOI

10.1109/FPGA.1995.477412

Filename

477412