Performance analysis of 1 bit full adder using GDI logic

Author

Mohan, Shoba ; Rangaswamy, Nakkeeran

Author_Institution

Dept. of Electron. Eng., Pondicherry Univ., Pondicherry, India

fYear

2014

fDate

27-28 Feb. 2014

Firstpage

1

Lastpage

4

Abstract

This paper focuses on the design of 1 bit full adder circuit using Gate Diffusion Input Logic. The proposed adder schematics are developed using DSCH2 CAD tool, and their layouts are generated with Microwind 3 VLSI CAD tool. A 1 bit adder circuits are analyzed using standard CMOS 120nm features with corresponding voltage of 1.2V. The Simulated results of the proposed adder is compared with those of Pass transistor, Transmission Function, and CMOS based adder circuits. The proposed adder dissipates low power and responds faster.

Keywords

CMOS logic circuits; VLSI; adders; logic CAD; DSCH2 CAD tool; GDI logic; Microwind 3 VLSI CAD tool; full adder circuit design; gate diffusion input logic; low-power dissipation; performance analysis; size 120 nm; standard CMOS features; transmission function; voltage 1.2 V; word length 1 bit; Adders; CMOS integrated circuits; Delays; Logic gates; Power demand; Transistors; Very large scale integration; adder; full swing; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Communication and Embedded Systems (ICICES), 2014 International Conference on

Conference_Location

Chennai

Print_ISBN

978-1-4799-3835-3

Type

conf

DOI

10.1109/ICICES.2014.7034029

Filename

7034029