Variability in nano-scale intrinsic silicon-on-thin-box MOSFETs (SOTB MOSFETs)

Lightly doped or even intrinsic channel can be used in SOTB MOSFETs and therefore very Low RDF (random dopant flunctuation) can be expected in such devices. In this work, we systematically investigated the influences of the intrinsic parameter fluctuations, including LER (line-edge-roughness), STV (silicon thickness variation) and WFV (metal-gate work-function variation), on 20nm-gate intrinsic SOTB MOSFETs with GP (ground plane). Conditions of SOTB without GP and with PGP (partial ground plane) are also simulated for comparison. Our results show that LER dominates fluctuations in n-SOTB while LER and WFV dominate that in p-SOTB. Introduction of GP can effectively reduce LER- and STV-induced variations of V_tsat, DIBL and I_on with a slightly sacrifice of σLog(I_off) while it has little effect on WFV-induced variations. A detailed design of PGP is desired from the perspective of variability-aware optimization.