DocumentCode :
2611504
Title :
Managing a Massively-Parallel Resource-Constrained Computing Architecture
Author :
Patterson, Cameron ; Preston, Thomas ; Galluppi, Francesco ; Furber, Steve
Author_Institution :
Univ. of Manchester, Manchester, UK
fYear :
2012
fDate :
5-8 Sept. 2012
Firstpage :
723
Lastpage :
726
Abstract :
One approach to creating a massively-parallel high-performance machine is to use large quantities of power-efficient processors, primarily due to the energy consumption of conventional high-performance computing designs. SpiNNaker is a novel high-performance architecture formed by large numbers of highly-interconnected low-power processing elements, more typically found in embedded systems. This paper presents the results of the implementation of a low-overhead management framework enabled by a universal translation layer: SpiNNmate. SpiNNmate is located between a SpiNNaker machine and the communication protocols of external applications, and we include results from a translation of the standards-based SNMP protocol to SpiNNaker.
Keywords :
embedded systems; parallel architectures; power aware computing; protocols; SpiNNaker machine; SpiNNmate; communication protocols; embedded systems; energy consumption; high-performance computing designs; highly-interconnected low-power processing elements; low-overhead management framework; massively-parallel high-performance machine; massively-parallel resource-constrained computing architecture; power-efficient processors; standards-based SNMP protocol; universal translation layer; Computer architecture; Databases; Hardware; Monitoring; Protocols; Software; Temperature sensors; Computer performance; Embedded; High performance computing; Middleboxes; Monitoring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital System Design (DSD), 2012 15th Euromicro Conference on
Conference_Location :
Izmir
Print_ISBN :
978-1-4673-2498-4
Type :
conf
DOI :
10.1109/DSD.2012.84
Filename :
6386963
Link To Document :
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