DocumentCode
2611549
Title
High performance graphics on a SIMD linear processor array
Author
Letellier, Laurent ; Juvin, Didier ; Rebillat, Jean ; Basille, Jean-Luc
Author_Institution
LETI DEIN, Gif sur Yvette, France
fYear
1993
fDate
3-6 May 1993
Firstpage
1901
Abstract
The specific features of a single instruction, multiple data (SIMD) parallel architecture applied to graphics through line drawing algorithms are discussed. This cost-effective graphics accelerator represents an alternative to dedicated hardware. The main features of the SYMPAT12 system are presented. The line drawing methods validated on the calculator as well as their performances are described. The results demonstrate the validity of this architecture applied to graphics
Keywords
computer graphics; parallel architectures; parallel machines; SIMD linear processor array; SYMPAT12 system; graphics accelerator; line drawing algorithms; parallel architecture; Collaboration; Delay; Graphics; Hardware; Image processing; Manufacturing; Parallel machines; Parallel processing; Scalability; Workstations;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location
Chicago, IL
Print_ISBN
0-7803-1281-3
Type
conf
DOI
10.1109/ISCAS.1993.394120
Filename
394120
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