Redundant algebra and integrated circuit implementation of ternary logic and their applications

A new algebra called redundant algebra is proposed and analyzed for the design of the ternary logic systems. The ternary systems can be realized by dynamic CMOS logic circuits. A new dynamic differential logic called CMOS redundant differential logic (CRDL) is developed to increase the logic flexibility and the circuit performance. The multiplier with redundant binary addition (RBA) tree is designed in both synchronous and pipelined systems. The synchronous RBAs designed by using CRDL circuits show better speed performance than other proposed static RBAs. The pipelined multiplier designed by using the true-single-phase-clock (TSPC) scheme has higher operating frequency and less pipelined stages as compared to the conventional binary parallel pipelined multiplier. The experimental chip is fabricated and measured. This successfully verifies the correctness of the logic functions and the advantage in speed performance of the designed circuits