Data-stationary controller for 32-bit application-specific RISC

A modified data-stationary controller for reduced instruction set computer (RISC) to support multi-cycle instructions and instruction prefetching and achieve precise exceptions is described. It is confirmed through performance evaluation that the authors´ modified data-stationary controller has higher operating frequency, shorter routing path, and smaller hardware than time-stationary controllers and data-stationary controllers using internal op-code. This controller is used as the controller for a 32-bit application-specific RISC with forty-six instructions and 8-bit op-code. The measured results for a fabricated chip show that the controller can be applied to RISC microprocessors with a clock frequency of up to 60 MHz