Compact process and layout aware model for variability optimization of circuit in nanoscale CMOS

Author

Kim, Yo-Han ; Jeon, Jong-Wook ; Jang, Yong-Un ; Park, Yong-Hee ; Yang, Gi-Young ; Park, Young-Kwan ; Yoo, Moon-Hyun ; Chung, Chil-Hee

Author_Institution

Semicond. R&D Center, Samsung Electron. Co., Ltd., Hwasung, South Korea

fYear

2010

fDate

6-8 Sept. 2010

Firstpage

141

Lastpage

144

Abstract

A predictive MOSFET model is very critical for early circuit design in nanoscale CMOS technologies. In this work, we developed a new compact MOSFET model which can dramatically improve the predictability of BSIM4 for the major 3 process and 2 layout variations by applying the simple physics-based equations to model these parameters. The accuracy of the model is verified using numerical TCAD simulation results and measurements under full range of temperature and bias conditions. The compact model for the circuit simulation can be efficiently used to predict the effects of process and layout variations on the circuit characteristics.

Keywords

MOSFET; SPICE; circuit simulation; optimisation; technology CAD (electronics); circuit simulation; compact process; layout aware model; nanoscale CMOS; numerical TCAD simulation results; predictive MOSFET model; variability optimization; Integrated circuit modeling; Layout; Mathematical model; Numerical models; Predictive models; Semiconductor device modeling; Semiconductor process modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices (SISPAD), 2010 International Conference on

Conference_Location

Bologna

ISSN

1946-1569

Print_ISBN

978-1-4244-7701-2

Electronic_ISBN

1946-1569

Type

conf

DOI

10.1109/SISPAD.2010.5604545

Filename

5604545