Title :
Halo profile engineering to reduce Vt fluctuation in high-k/metal-gate nMOSFET
Author :
Chen, W.-Y. ; Yu, T.-H. ; Ohtou, Tetsu ; Sheu, Y.-M. ; Wu, Jeff ; Liu, CheeWee
Author_Institution :
TCAD Div., Taiwan Semicond. Manuf. Co. (TSMC), Taiwan
Abstract :
In this work, new halo profile engineering is proposed to suppress the threshold voltage variation (σVt) caused by discrete random dopant fluctuation (RDF). An in-house 3D atomistic numerical simulation tool is utilized to assess nMOSFETs σVt caused by RDF for a HK/MG process. The results show that σVt can be effectively suppressed by 10% by optimizing rotation and tilt angles of the halo implant.
Keywords :
CMOS integrated circuits; MOSFET; numerical analysis; semiconductor doping; discrete random dopant fluctuation; halo profile engineering; high-k/metal-gate nMOSFET; in-house 3D atomistic numerical simulation tool; threshold voltage variation suppression; Fluctuations; Implants; Logic gates; Resource description framework; Semiconductor process modeling; Solid modeling; Three dimensional displays; high-k/metal gate; random dopant fluctuation; variability;
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2010 International Conference on
Conference_Location :
Bologna
Print_ISBN :
978-1-4244-7701-2
Electronic_ISBN :
1946-1569
DOI :
10.1109/SISPAD.2010.5604546
