Robust Evaluation of Weighted Random Logic BIST Structures in Industrial Designs

This paper presents a highly robust approach to exactly analyze signal probabilities of Weighted Random Logic (WRL) BIST structures. WRL BIST structures are implemented in modern CMOS designs to ensure high defect coverage for example during on-line in-system tests, which are executed periodically in safety applications as needed in automotive designs. Furthermore the paper describes a novel design flow which automatically identifies and evaluates WRL BIST structures in large industrial designs. The complete design flow from calculating the weighted random logic up to its automatic identification and evaluation in pre- and post-layout netlists is discussed in detail. The effectiveness of the new approach has been evaluated on 10 industrial designs and various other test cases. The results show that the memory consumption of the proposed technique does not grow despite of an immense increase of the circuit size.