Time efficient method for MOS circuit extraction

Author

Doerffer, Karol ; Anton, Oskar ; Mlynski, Dieter A.

Author_Institution

Inst. fuer Theoretische Elektrotech. & Messtech., Karlsruhe, Univ., Germany

fYear

1993

fDate

3-6 May 1993

Firstpage

1983

Abstract

A new method for circuit extraction from VLSI masks for any MOS technology is presented. The algorithms operate on mask edges allowing rapid connectivity and device extraction. A new approach to non rectilinear polygon overlap analysis is presented. The scanline algorithm used is modified to meet geometric features imposed by technology. The transistor extraction is based on analysis of oriented, polygonal forms, allowing simultaneous transistor recognition and extraction of its topological parameters. The algorithms enable faster circuit extraction than previously presented methods, and, at the same time, are easy to understand and to implement

Keywords

MOS integrated circuits; SPICE; VLSI; circuit layout CAD; masks; network parameters; network topology; MOS circuit extraction; VLSI masks; device extraction; geometric features; mask edges; non rectilinear polygon overlap analysis; polygonal forms; rapid connectivity; scanline algorithm; topological parameters; transistor extraction; transistor recognition; Algorithm design and analysis; Circuit analysis; Circuit testing; Contacts; Data mining; Geometry; Integrated circuit interconnections; Optimization methods; Shape; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394141

Filename

394141