Test generation for BiCMOS circuits

Author

Menon, Sankaran M. ; Jayasumana, Anura P. ; Malaiya, Yashwant K.

Author_Institution

Colorado State Univ., Ft. Collins, CO, USA

fYear

1993

fDate

3-6 May 1993

Firstpage

1987

Abstract

Stuck-ON faults in BiCMOS devices result in an enhanced I_DDQ. Stuck-OPEN faults exhibit both sequential behavior and delay faults. Test generation is considered for stuck-ON and stuck-OPEN faults in BiCMOS circuits. A procedure for obtaining test vectors/sequences for testing of faults manifesting as enhanced I_DDQ delay faults and sequential behavior is presented. The procedure involves activating a conduction path to obtain test vectors/sequences. The resulting test vectors obtained for single stuck-ON faults are also applicable to multiple stuck-ON faults. The scheme provides robust test sequences with unity Hamming distance for testing of delay faults and sequential behavior in BiCMOS circuits

Keywords

BiCMOS digital integrated circuits; Hamming codes; binary sequences; delays; fault diagnosis; integrated circuit testing; mixed analogue-digital integrated circuits; BiCMOS circuits; conduction path; delay faults; robust test sequences; sequential behavior; stuck-ON faults; stuck-OPEN faults; test vectors; unity Hamming distance; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Delay; Integrated circuit modeling; Semiconductor device modeling; Sequential analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394142

Filename

394142