Implementation of a low power LDPC decoder using bit serial architecture

A bit serial architecture is used which reduces the interconnect complexity in fully parallel low density parity check (LDPC) decoder. This can achieve better error correcting performance when the code length is moderate. By using a new approximation to the check update function in the Minsum decoding algorithm, the implementation is simplified. This new check update rule finds only the absolute minimum magnitude of the incoming message and if required correction is made to the outgoing messages. The proposed decoder is designed using Verilog HDL, simulated using MODELSEVI 5.7g, synthesized by Xilinx 9.2i and implemented using Spartan 3E. The result shows that the proposed architecture requires fewer slices and LUT´s when compared with the existing methods.