Parallel implementation of a cut and paste maze routing algorithm

Author

Kumar, H. ; Kalyan, R. ; Bayoumi, M. ; Tyagi, A. ; Ling, N.

Author_Institution

Intel Corp., Beaverton, OR, USA

fYear

1993

fDate

3-6 May 1993

Firstpage

2035

Abstract

Wire routing is a compute bound phase in the design of VLSI circuits. Some of the software solutions to this problem entail divide and conquer methods, such as hierarchical routing, in order to reduce its time complexity. Hardware accelerators have been employed to achieve further increase in the speed of this process. Implementation aspects of a reduced array architecture (RAA) for hardware acceleration of the cut and paste hierarchical routing algorithm are detailed. Several macros are defined to implement the algorithm in hardware. The architecture is implemented in double-metal 2-μ CMOS technology

Keywords

CMOS digital integrated circuits; VLSI; circuit layout CAD; computational complexity; network routing; parallel architectures; 2 micron; CMOS technology; VLSI circuits; cut and paste maze routing algorithm; hardware accelerators; hierarchical routing; parallel architectures; reduced array architecture; time complexity; wire routing; Acceleration; CMOS technology; Circuits; Computer architecture; Engines; Hardware; Physics computing; Routing; Very large scale integration; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on

Conference_Location

Chicago, IL

Print_ISBN

0-7803-1281-3

Type

conf

DOI

10.1109/ISCAS.1993.394154

Filename

394154