DocumentCode
261231
Title
A 1V second order delta sigma ADC in 130nm CMOS
Author
Krishna, K. Lokesh ; Ramashri, T. ; Reena, D.
Author_Institution
Dept. of ECE, Sri Venkateswara Coll. of Eng. & Technol., Chittoor, India
fYear
2014
fDate
27-28 Feb. 2014
Firstpage
1
Lastpage
5
Abstract
Sigma-Delta modulators are commonly used in applications that require high resolution. In this paper a IV second order sigma delta ADC is presented. In this paper over sampling concept is used to address the problem of power dissipation and noise in ADCs. A second order sigma delta modulator is implemented using CMOS 130nm technology. Oversampling ratio is 128 and total power dissipation is found to be 68μW and area occupied is found to be 24μm ×30μm.
Keywords
CMOS integrated circuits; circuit noise; integrated circuit design; sigma-delta modulation; ADC noise; CMOS; IV second order sigma delta ADC; power 68 muW; power dissipation; sigma-delta modulators; size 130 nm; size 24 mum; size 30 mum; CMOS integrated circuits; CMOS technology; Educational institutions; Modulation; Noise; Operational amplifiers; Sigma-delta modulation; 130nm; ADC; high speed; low power; low voltage and over sampling ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Communication and Embedded Systems (ICICES), 2014 International Conference on
Conference_Location
Chennai
Print_ISBN
978-1-4799-3835-3
Type
conf
DOI
10.1109/ICICES.2014.7034116
Filename
7034116
Link To Document