Optimum gate voltage search for junctionless Tunnel FET using TCAD simulations

Author

Vadivukkarasi, J. ; Kumar, N. Vinodh ; Nagarajan, K.K. ; Srinivasan, R.

Author_Institution

ECE Dept., SSN Coll. of Eng., Chennai, India

fYear

2014

fDate

27-28 Feb. 2014

Firstpage

1

Lastpage

6

Abstract

The Structure of n type junctionless Tunnel FET is created and its characteristic is studied using TCAD simulations. The device simulations have been implemented with different voltage levels for different gate structures present in the device-gate over drain (V_G1) and gate over source (V_G2), and the transfer characteristics (I_D-V_G) are studied. Considering drive current (I_on)> off current (I_off)> I_on/I_off ratio, and subthreshold slope as metric, an optimum level of V_G1 and V_G2 is seen for the device.

Keywords

field effect transistors; logic CAD; TCAD simulation; device-gate over drain; drive current; field effect transistors; gate over source; gate voltage search; junctionless tunnel FET; off current; transfer characteristics; transistor computer aided design; Educational institutions; Logic gates; MOSFET; Performance evaluation; Semiconductor process modeling; Tunneling; Band-to-Band Tunneling; Junctionless Tunnel FET; TCAD;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Communication and Embedded Systems (ICICES), 2014 International Conference on

Conference_Location

Chennai

Print_ISBN

978-1-4799-3835-3

Type

conf

DOI

10.1109/ICICES.2014.7034121

Filename

7034121