• DocumentCode
    2613486
  • Title

    Polyimide Interlevel Insulation Process/Design Limitations

  • Author

    Bergeron, D.L. ; Kent, J.P. ; Morrett, K.E.

  • Author_Institution
    IBM General Technology Division, Essex Junction, VT 05452
  • fYear
    1984
  • fDate
    30773
  • Firstpage
    229
  • Lastpage
    233
  • Abstract
    This paper describes a polyimide interlevel metal insulation process. The use of polyimide near high voltage devices can result in anomalous leakage in certain regions at elevated temperatures. The paper summarizes the reliability investigation on discrete devices fabricated with polyimide, as the interlevel material, as well as characterization data which support design criteria permitting the use of polyimide as an interlevel insulation material.
  • Keywords
    Etching; Insulation; Materials reliability; Plasma applications; Plasma temperature; Polyimides; Process design; Resists; Silicon; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 1984. 22nd Annual
  • Conference_Location
    Las Vegas, NV, USA
  • ISSN
    0735-0791
  • Type

    conf

  • DOI
    10.1109/IRPS.1984.362051
  • Filename
    4208575